1. Technical Field
The present invention relates to programmable logic devices and, more particularly, to creating an event interface for a processor using a programmable logic device.
2. Description of the Related Art
Electronic circuit designs can be constructed, simulated, debugged, and translated into electronic hardware using a High Level Modeling System (HLMS). Typically, an HLMS is implemented as a software-based design tool which provides blocks that can be combined to build an electronic circuit. A block, also called a module, refers to a high level software construct that represents a particular circuit function, such as multiplexing, addition, multiplication, or the like. Blocks may have ports that can produce and consume signals, and may be arranged within the HLMS to form a circuit and/or system. Communication among the blocks can be represented by wires, or signals, that graphically link the blocks. The design may be simulated within the HLMS once it is constructed. Some HLMS tools can generate a hardware implementation from the block representation of the circuit design. For example, an HLMS may generate the bitstream necessary to program a programmable logic device (PLD) or generate the hardware description language (HDL) files necessary to specify the hardware design.
PLDs are a well-known type of integrated circuit. A PLD can be programmed by a user to perform specified logic functions. There are different types of PLDs, such as programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs). An FPGA, for example, typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure can be programmed by loading a stream of configuration data, referred to as a bitstream, into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers. Other types of FPGAs may have different structures or architectures, and may include other types of resources, both programmable and non-programmable, and are well-known to those of skill in the art.
One example of an HLMS is System Generator for DSP, available from Xilinx, Inc. of San Jose, Calif. System Generator for DSP is a system level modeling tool that facilitates FPGA hardware design. System Generator for DSP provides a wide range of blocks that can be automatically compiled into a design suitable for an FPGA. Among these blocks are high level abstractions that implement complex functions, including digital signal processing as well as communication and control logic. In addition, access to underlying FPGA resources can be provided through low level block abstractions that facilitate the construction of highly efficient FPGA designs.
As noted above, FPGAs can include processors that are embedded on the device. Such processors can include a microprocessor core, as well as associated control logic. An embedded processor can include embedded hardware or embedded firmware or a combination thereof for a “hard” or “soft” microprocessor. A soft microprocessor can be implemented using the programmable logic (e.g., CLBs, IOBs). For example, a MicroBlaze™ soft microprocessor, available from Xilinx, Inc., may be employed. A hard microprocessor can be implemented using an IBM POWER PC™, Intel PENTIUM™, AMD ATHLON™, or like type of processor core known in the art.
When a processor is incorporated into a circuit design, whether embedded on the PLD or located “off-chip”, interrupts must be defined that inform the processor when a particular event has occurred that requires the attention of the processor. Typically, interrupts are generated or raised by peripherals. In the context of an FPGA, a peripheral can refer to user logic or other devices. The particular reason why an interrupt is raised can vary, but examples can include, a first-in-first-out memory (FIFO) being full and requiring a read operation, a FIFO is nearly full and instruction from the processor is needed, or the like.
Processors, whether implemented on an FPGA or as a standalone processor, have a limited number of interrupt ports. Peripherals and other devices that generate interrupt signals must share these ports. Accordingly, one aspect of designing a system that includes a processor is creating an interface that can manage the interrupts being provided to the processor. When more than one interrupt is generated, the interface must collect interrupt signals and prioritize those signals according to importance.
Creating this interrupt interface to the processor can be a tedious and time consuming task. The circuit designer must manage a large amount of hardware and software control logic and/or code. A similar situation exists with respect to direct memory access (DMA) events. A DMA event refers to the case where data is to be transferred between memory and another peripheral device. A DMA transfer typically involves a DMA controller, which can be considered a particular type, or special purpose, type of processor. Memories requiring a DMA action submit DMA requests to the DMA controller asking for the DMA event to be initiated.